This invention relates to cache memories and, more particularly, to an improved system for accessing data in cache memories reducing the cycle time, and chip area required for some of the addressing hardware. The system also facilitates processing fetch instructions in parallel.
A cache memory, or cache, is a high speed memory positioned between a data processor and main storage to hold recently accessed main storage data. Whenever data in storage is accessed, it is first determined whether or not the data is in the cache and, if so, it is accessed from the cache. If the data is not in the cache, then the data is obtained from the main storage and the data is also stored in the cache usually replacing other data which had been stored in the cache memory.
The present invention is designed to be used in a data processing system, such as the IBM System/9000 High End Processor. In this data processing system, more than one data processing unit can fetch data from a cache. Since the data in the cache can be stored-to after it has been prefetched, it is necessary to determine, when storing new data in a cache, whether the same address has been previously fetched by a different data processing unit so that the different data processing unit can be notified that the fetched data may be obsolete or invalid. For this purpose, the data processing system carries out a comparison function called an operand store compare, or OSC, whenever data is stored in the cache by a data processing unit, such as a CPU. In the OSC comparison function, the store address is compared with the fetch addresses which will have been saved at the time the operands were previously fetched. In a similar manner, whenever data is stored in the cache, the system performs a comparison function called a program store compare, or PSC, in which the store address is compared with the fetch address of previously fetched instructions to determine if the instruction has been previously fetched. Because of the number of bits involved in the addresses, the comparison process can cause timing problems and also can be inaccurate.
The present invention saves time, increases the accuracy of the OSC and PSC, and reduces the area required on the integrated circuit chip for the OSC and PSC functions. In addition, the present invention facilitates fetches from the same line as previous fetches by enabling them to be carried out without accessing the look-aside buffers, such as the TLB (translation look-aside buffer) and ALB (access register translation look-aside buffer) or the cache directory and enabling fetches to be carried out in parallel.